 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| I C R O C LOC K Description The MK2745-24 is a low cost, low jitter, high performance clock synthesizer for DVD and other MPEG 2 based applications. Using analog PhaseLocked Loop (PLL) techniques, the device accepts a 27.00 MHz fundamental mode crystal or clock input to produce multiple audio output clocks, a processor clock, and two 27 MHz clocks. The audio clocks are frequency locked to the 27.00 MHz using our patented zero ppm error techniques, allowing audio and video to track exactly, thereby eliminating the need for large buffer memory. MicroClock manufactures the largest variety of DVD, Set-Top Box, and multimedia clock synthesizers for all applications. Consult MicroClock to eliminate crystals and oscillators from your board. MK2745-24 DVD/MPEG Clock Source Features * Packaged in 16 pin narrow (150 mil) SOIC * Ideal for AuraVision's notebook DVD solutions * Patented zero ppm audio clock error for exact audio clock sampling rates, plus 32x and 256x clocks of the sampling frequencies * Selectable audio sampling frequencies support 32, 44.1, 48 and 96 kHz in most DACs * 27.00 MHz fundamental crystal or clock input * Selectable processor frequencies * Two clocks of 27 MHz * Zero ppm error in all clocks * 25mA output drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * 3.0V to 5.5V operating voltage * See also the MK2712 for NTSC/PAL clocks Block Diagram VDD 2 /2 GND 3 Output Buffer ACS1:0 PCS PCLK ACLK ACLK/8 ACLK/256 27.0 MHz 27.0 MHz Clock Synthesis and Control Circuitry 27 MHz clock or crystal X1 Crystal Oscillator X2 Output Buffer /8 /256 Output Buffer Output Buffer Output Buffer Output Buffer 1 Revision 100898 Printed 11/16/00 MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax MDS 2745-24 B I C R O C LOC K Pin Assignment MK2745-24 GND X2 X1/ICLK VDD GND 27M ACS0 ACLK/8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ACS1 27M PCLK VDD GND ACLK PCS ACLK/256 MK2745-24 DVD/MPEG Clock Source Audio Clocks Selection Table (in MHz) ACS1 ACS0 0 0 1 1 0 1 0 1 ACLK 24.576 11.2896 8.192 12.288 ACLK/8 3.072 1.4112 1.024 1.536 ACLK/256 96.0 kHz 44.1 kHz 32.0 kHz 48.0 kHz Processor Clock (MHz) PCS 0 1 PCLK 40 60 16 pin (150 mil) SOIC Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name GND X2 X1/ICLK VDD GND 27M ACS0 ACLK/8 ACLK/256 PCS ACLK GND VDD PCLK 27M ACS1 Type P XO XI P P O I O O I O P P O O I 0 = connect directly to ground 1 = connect directly to VDD Description Connect to ground. Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock input. Crystal connection. Connect to 27 MHz crystal or connect to 27 MHz input clock. Connect to +3.3 V or +5 V. Must be same as other VDD. Connect to ground. 27.00 MHz clock output. Audio Clock Select 0. Selects audio clocks per table above. Audio Clock divided by 8 output. Determined by status of ACS1, ACS0. See table above. Audio Clock divided by 256 output. Determined by status of ACS1, ACS0. See table above. Processor Clock Select pin. Selects PCLK per table above. Audio Clock output. Determined by status of ACS1, ACS0. See table above. Connect to ground. Connect to +3.3 V or +5 V. Must be same as other VDD. Processor Clock output. Determined by status of PCS. See table above. 27.00 MHz clock output. Audio Clock Select 1. Selects audio clocks per table above. Key: I = Input, O = output, P = power supply connection 2 Revision 100898 Printed 11/16/00 MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax MDS 2745-24 B I C R O C LOC K Electrical Specifications Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Operating Voltage, VDD Input High Voltage, VIH, X1/ICLK pin only Input Low Voltage, VIL, X1/ICLK pin only Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Short Circuit Current Input Capacitance Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Frequency synthesis error, all clocks Absolute Jitter, short term Notes: Conditions Referenced to GND Referenced to GND Max of 20 seconds MK2745-24 DVD/MPEG Clock Source Minimum Typical Maximum 7 VDD+0.5 70 260 150 5.5 VDD/2 VDD/2 VDD/2 - 1 0.8 Units V V C C C V V V V V V V V mA mA pF MHz ns ns % ppm ps ABSOLUTE MAXIMUM RATINGS (note 1) -0.5 0 -65 3 VDD/2 + 1 2 IOH=-25mA IOL=25mA IOH=-8mA No Load, note 2 Each output 2.4 0.4 VDD-0.4 37 100 7 27.000 0.8 to 2.0V 2.0 to 0.8V At VDD/2 Variation from mean 1.5 1.5 60 1 DC CHARACTERISTICS (VDD = 5.0V unless noted) AC CHARACTERISTICS (VDD = 5.0V unless noted) 40 0 200 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With VDD=3.3V, processor clock at 60MHz, and ACLK at 12.288MHz. External Components The MK2745-24 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1F should be connected between VDD and GND (on pins 4 and 5, and pins 13 and 12), as close to the MK2745-24 as possible. A series termination resistor of 33 may be used for each clock output. If a clock input is not used, the 27.00 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use third overtone), parallel resonant, 50ppm or better. Crystal capacitors should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL -6) x 2. So for a crystal with 16pF load capacitance, two 20pF caps should be used. 3 Revision 100898 Printed 11/16/00 MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax MDS 2745-24 B I C R O C LOC K Package Outline and Package Dimensions MK2745-24 DVD/MPEG Clock Source 16 pin SOIC narrow Symbol A b c D E H e h Q Inches Min Max 0.055 0.070 0.013 0.019 0.007 0.010 0.385 0.400 0.150 0.160 0.225 0.245 .050 BSC 0.016 0.004 0.01 Millimeters Min Max 1.397 1.778 0.330 0.483 0.191 0.254 9.779 10.160 3.810 4.064 5.715 6.223 1.27 BSC 0.406 0.102 0.254 E H D Q e b c h x 45 A Ordering Information Part/Order Number MK2745-24S MK2745-24STR Marking MK2745-24S MK2745-24S Shipping packaging tubes tape and reel Package Temperature 16 pin narrow SOIC 0-70C 16 pin narrow SOIC 0-70C Rev. 04218, version A . First publication, Preliminary. Rev. 10088, version B. Production. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 4 Revision 100898 Printed 11/16/00 MicroClock Division of ICS*1271 Parkmoor Ave.*San Jose*CA*95126*(408)295-9800tel*(408)295-9818fax MDS 2745-24 B |
Price & Availability of MK2745-24
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |